Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits

Authors:
Jie Zhang;Nishant P. Patil;Subhasish Mitra
Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Computer Science, Stanford University, Stanford, CA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

Metallic carbon nanotubes (CNTs) pose a major barrier to the design of digital logic circuits using CNT field-effect transistors (CNFETs). Metallic CNTs create source to drain shorts in CNFETs, resulting in undesirable effects such as excessive leakage and degraded noise margins. No known CNT growth technique guarantees 0% metallic CNTs. Therefore, special processing techniques are required for removing metallic CNTs after CNT growth. This paper presents a probabilistic model which incorporates processing and design parameters and enables quantitative analysis of the impact of metallic CNTs on leakage, noise margin, and delay variations of CNFET-based digital logic circuits. With practical constraints on these key circuit performance metrics, the model provides design and processing guidelines that are required for very large scale integration (VLSI)-scale metallic-CNT-tolerant digital circuits.