Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Authors:
Gage Hills;Jie Zhang;Charles Mackin;Max Shulaker;Hai Wei;H.-S. Philip Wong;Subhasish Mitra
Affiliations:
Stanford University, CA;Google, Inc.;Massachusetts Institute of Technology, MA;Stanford University, CA;Stanford University, CA;Stanford University, CA;Stanford University, CA
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

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Abstract

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad-hoc techniques. In this paper, we present a systematic framework which quickly evaluates the impact of CNT variations on circuit delay and noise margin, and automatically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that: 1. Our new framework runs over 100X faster than existing approaches. 2. It accurately identifies the most important CNT processing parameters, together with CNFET circuit sizing, to minimize the impact of CNT variations while meeting circuit-level noise margin constraints.