Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes

Authors:
N. Patil;A. Lin;J. Zhang; Hai Wei;K. Anderson;H. -S.P. Wong;S. Mitra
Affiliations:
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA;-;-;-;-;-;-
Venue:
IEEE Transactions on Nanotechnology
Year:
2011

Citing 0
Cited 4

Carbon nanotube imperfection-immune digital VLSI: frequently asked questions updated

Proceedings of the International Conference on Computer-Aided Design
Carbon nanotube circuits: opportunities and challenges

Proceedings of the Conference on Design, Automation and Test in Europe
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Proceedings of the 50th Annual Design Automation Conference
Sacha: the Stanford carbon nanotube controlled handshaking robot

Proceedings of the 50th Annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a new very large scale integration (VLSI)-compatible metallic carbon nanotube (CNT) removal technique called VLSI-compatible metallic CNT removal (VMR) that overcomes challenges of existing techniques by combining design and processing to create carbon nanotube field effect transistors (CNFET) circuits immune to CNT imperfections such as metallic and mispositioned CNTs. Using VMR, we experimentally demonstrate combinational and sequential CNFET logic circuits such as half-adder sum generators and D-latches. These circuits form the fundamental building blocks of VLSI digital systems.