Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and comparing CMOS implementations of the C-element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing C-elements is not elementary
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
CMOS Scaling for sub-90 nm to sub-10 nm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Automated design of misaligned-carbon-nanotube-immune circuits
Proceedings of the 44th annual Design Automation Conference
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications
Proceedings of the 45th annual Design Automation Conference
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Asynchronous Nano-Electronics: Preliminary Investigation
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
Performance estimation and slack matching for pipelined asynchronous architectures with choice
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Carbon nanotube circuits in the presence of carbon nanotube density variations
Proceedings of the 46th Annual Design Automation Conference
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Is Asynchronous Logic More Robust Than Synchronous Logic?
IEEE Transactions on Dependable and Secure Computing
Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs
Electronic Notes in Theoretical Computer Science (ENTCS)
Diagnosis of faults in template-based asynchronous circuits
SOC'09 Proceedings of the 11th international conference on System-on-chip
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Designer's Guide to Asynchronous VLSI
A Designer's Guide to Asynchronous VLSI
Carbon nanotube circuits: living with imperfections and variations
Proceedings of the Conference on Design, Automation and Test in Europe
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
IEEE Transactions on Nanotechnology
Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of Defects
IEEE Transactions on Nanotechnology
A timing-constrained simultaneous global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of hazard-free asynchronous circuits with bounded wire delays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: the Muller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations.