IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
IEEE Design & Test
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions.