Communication and concurrency
Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Theoretical Computer Science
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis and verification of timed asynchronous circuits
Timing analysis and verification of timed asynchronous circuits
Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Static timing analysis for self resetting circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Modeling and comparing CMOS implementations of the C-element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automatic Synthesis of Fast Compact Asynchronous Control Circuits
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Two-Phase Asynchronous Pipeline Control
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
Polynomial-time techniques for approximate timing analysis of asynchronous systems
Polynomial-time techniques for approximate timing analysis of asynchronous systems
POSET timing and its application to the synthesis and verification of gate-level timed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed circuit verification using TEL structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic synthesis of computation interference constraints for relative timing verification
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Asynchronous computing in low power based sense amplifier pass transistor logic
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous computing in sense amplifier-based pass transistor logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Relativistic Causality and Clockless Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Time aware modelling and analysis of multiclocked VLSI systems
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Timing verification of gasp asynchronous circuits: predicted delay variations observed by experiment
Concurrency, Compositionality, and Correctness
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Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3 × in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated.