Computer-aided synthesis and verification of gate-level timed circuits

Lazy transition systems: application to timing optimization of asynchronous circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

CAD directions for high performance asynchronous circuits

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Semi-modular Latch Chains for Asynchronous Circuit Design

PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation

Relative timing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

RAPPID: An Asynchronous Instruction Length Decoder

ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Relative Timing

ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Verification of Delayed-Reset Domino Circuits Using ATACS

ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline

ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Automatic synthesis of computation interference constraints for relative timing verification

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design

Effective contraction of timed STGs for decomposition based timed circuit synthesis

ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis

A compositional minimization approach for large asynchronous design verification

SPIN'12 Proceedings of the 19th international conference on Model Checking Software