Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Checking properties of nets using transformation
Advances in Petri Nets 1985, covers the 6th European Workshop on Applications and Theory in Petri Nets-selected papers
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
High Level Synthesis of Timed Asynchronous Circuits
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Covering conditions and algorithms for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a way to contract timed STGs effectively for a decomposition based logic synthesis of timed circuits. In the decomposition based synthesis method, a sufficient input signal set for each output is first obtained, and the timed STG is contracted to include only transitions on this input signal set and the output of interest, from which the circuit for the output is synthesized. Care is, however, needed for the contraction of timed STGs. A simple contraction algorithm used for the untimed version can result in the loss of important timing information, causing it to synthesize non-optimal circuits. On the other hand, exact contraction that preserves the timing information precisely is applied only to a small class of transitions, which degrades the performance of the decomposition based synthesis method. This paper proposes a way to contract timed STGs effectively without losing the optimality of the synthesized circuits, and shows some experimental results.