Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On timed components and their abstraction
Proceedings of the 2007 conference on Specification and verification of component-based systems: 6th Joint Meeting of the European Conference on Software Engineering and the ACM SIGSOFT Symposium on the Foundations of Software Engineering
Path Compression in Timed Automata
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Automatic abstraction for verification of cyber-physical systems
Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical Systems
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective contraction of timed STGs for decomposition based timed circuit synthesis
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Path Compression in Timed Automata
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
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The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. Before verification is applied to each individual module, irrelevant information to the behavior of the selected module is abstracted away. This approach converts a verification problem with big exponential complexity to a set of subproblems, each with small exponential complexity. Experimental results are promising in that they indicate that our approach has the potential of completing much faster while using less memory than traditional flat analysis.