Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Efficient verification of determinate speed-independent circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Fast hazard detection in combinational circuits
Proceedings of the 41st annual Design Automation Conference
Verification of Concurrent Systems with Parametric Delays Using Octahedra
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from state-space explosion, or efficient algorithms which use (conservative) approximations to avoid state-space explosion, but have the drawback of a rather conservative definition of failure states, which results in the rejection of designs which are valid. Algorithms based on [1], extending it to the timed case [7], while being very efficient, are unable to handle circuits with internal loops, which prevents their use in some cases. We propose a new approach to the problem in order to overcome the mentioned limitations, without sacrificing efficiency. To do so, we first introduce a general framework targeted at the conservative checking of safety failures. This framework is not restricted to the checking of timed asynchronous circuits. Then, we propose a new (conservative) semantics to timed circuits, in order to use the proposed framework for hazard checking of such circuits. Using this framework with the proposed semantics yields an efficient algorithm that solves the limitations of the previous approaches.