Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Efficient Verification of Parallel Real–Time Systems
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
Proceedings of the 7th International Conference on Computer Aided Verification
STARI: A Case Study in Compositional and Hierarchical Timing Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of Timed Systems Using POSETs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.