Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Analysis and identification of speed-independent circuits on an event model
Formal Methods in System Design - Special issue on designing correct circuits
Efficient verification of determinate speed-independent circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Checking combinational equivalence of speed-independent circuits
Formal Methods in System Design
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Timed Circuits with Failure Directed Abstractions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
POSET timing and its application to the synthesis and verification of gate-level timed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed state space exploration using POSETs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an efficient method for verifying hazard freedomin timed asynchronous circuits. Timed circuits are a classof asynchronous circuits that utilize explicit timing informationfor optimization throughout the entire design process. In asynchronouscircuits, correct operation requires that there are no hazardsin the circuit implementation. Therefore, when designing anasynchronous circuit, each internal node and output of the circuitmust be verified for hazard-freedom to ensure correct operation.Current verification algorithms for timed asynchronous circuits requirean explicit state exploration often resulting in state explosionfor even modest sized examples. The goal of this work isto abstract the behavior of internal nodes and utilize this informationto make a conservative determination of hazard-freedom foreach node in the circuit. Experimental results indicate that thisapproach is substantially more efficient than existing timing verificationtools. These results also indicate that this method scaleswell for large examples. It is capable of analyzing circuits in lessthan a second that could not be previously analyzed. While thismethod is conservative in that some false hazards may be reported,our results indicate that the number of false hazards is small.