Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Partial Order Path Technique for Checking Parallel Timed Automata
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Symbolic Verification and Analysis of Discrete Timed Systems
Formal Methods in System Design
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Time Separation of Events: An Inverse Method
Electronic Notes in Theoretical Computer Science (ENTCS)
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This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSET's) to minimize the number of regions necessary. This algorithm operates on specifications sufficiently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing significant improvement in runtime and memory usage