Representing and modeling digital circuits
Representing and modeling digital circuits
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Partial Orders and Verification of Real-Time systems
FTRTFT '96 Proceedings of the 4th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
HYTECH: The Cornell HYbrid TECHnology Tool
Hybrid Systems II
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
POSET timing and its application to the synthesis and verification of gate-level timed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed state space exploration using POSETs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Layered composition for timed automata
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Performance evaluation of schedulers in a probabilistic setting
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Symbolically bounding the drift in time-constrained MSC graphs
ICTAC'12 Proceedings of the 9th international conference on Theoretical Aspects of Computing
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In a parallel composition of timed automata, some transitions are independent to others. Generally the basic method generates one successors for each of the legal permutations of the transitions. These successors may be combined into one bigger symbolic state. In other words, the basic algorithm slices one big symbolic state into pieces. The number of these pieces can be up to n!, where n is the number of independent transitions.In this paper, we introduce a concept, 'partial order path', to avoid treating the permutations one by one. A partial order path includes a set of transitions and a partial order on this set. Our algorithm generates one symbolic successor w.r.t. each partial order path. This big symbolic successor is just the combination of the successors w.r.t. all the global paths which are consistent to this partial order path. It is shown by some case studies that this method may result in significant space reduction.