Formal verification of pulse-mode asynchronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Proposal For Relative Time Petri Nets
SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Timing analysis of an embedded memory: SPSMALL
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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Delay-Insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations ...