Communicating sequential processes
Communicating sequential processes
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification of pulse-mode asynchronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
An efficient method for protocol conversion
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Process spaces and formal verification of asynchronous circuits
Process spaces and formal verification of asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
POSET timing and its application to the synthesis and verification of gate-level timed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we propose a novel refinement-based technique to formally verify data transfer in an asynchronous timing framework. Novel data transfer models are proposed to represent data communication between two locally independent clock domains. As a case study, we apply our technique to verify data transfer in a previously published architecture for globally asynchronous locally synchronous on-chip systems. In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected dangers.