Efficient state classification of finite state Markov chains
DAC '98 Proceedings of the 35th annual Design Automation Conference
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Optimal partitioning of globally asychronous locally synchronous processor arrays
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Integration, the VLSI Journal
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Exploring pausible clocking based GALS design for 40-nm system integration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
| Hi-index | 0.06 |
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshaking signals to the local module clock is done in an unconventional way -- the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshaking signal satisfies setup and hold time constraints with respect to the local clock. We constructed a test bed consisting of two synchronous modules with pausible clocking control and an asynchronous FIFO on a MOSIS 1.2um CMOS chip. The resulting system functions reliably up to the local clock frequency of 220MHz (according to SPICE simulation) -- the maximum clock rate is limited by the ring oscillator, not the pausible clocking control. Preliminary test results indicate that the fabricated chips operate correctly as simulated.