Two efficient synchronous ↔ asynchronous converters well-suited for networks-on-chip in GALS architectures

Authors:
A. Sheibanyrad;A. Greiner
Affiliations:
The University of Pierre and Marie Curie, 4, Place Jussieu, 75252 cedex 05, Paris, France;The University of Pierre and Marie Curie, 4, Place Jussieu, 75252 cedex 05, Paris, France
Venue:
Integration, the VLSI Journal
Year:
2008

Citing 16
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Abstract

This paper presents two high-throughput, low-latency converters that can be used to convert synchronous communication protocol to asynchronous one and vice versa. We have designed these two hardware components to be used in a Globally Asynchronous Locally Synchronous clusterized Multi-Processor System-on-Chip communicating by a fully asynchronous Network-on-Chip. The proposed architecture is rather generic, and allows the system designer to make various trade-offs between latency and robustness, depending on the selected synchronizer. We have physically implemented the two converters with portable ALLIANCE CMOS standard cell library and evaluated the architectures by SPICE simulation for a 90nm CMOS fabrication process.