A Solution to a Special Case of the Synchronization Problem
IEEE Transactions on Computers
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
Integration, the VLSI Journal
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A new method of retiming plesiochronous data is described. This method features latency of less than a cell-time and requires only minimal support circuitry. No flow control or handshaking signals are used, allowing true undirectional signalling between transmitter and receiver. Application areas include communication networks in parallel computers, and general communication network repeaters, hubs, bridges, and routers.