Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Digital systems engineering
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low-latency plesiochronous data retiming
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Synchronization circuits are essential in multi-clock-domain systems-on-chip. The most well-known synchronizer consists of two sequentially connected flip-flops that should eliminate the propagation of metastability into the receiver clock domain. We first clarify how such a simple "two-flop" synchronizer can be used in the system, and analyze its performance, showing that the data cycle may be as long as 12 clock cycles. Novel faster synchronizers are described next and their use and improved performance are explained. The fast synchronizer enable shorter data cycles, measuring only 2 to 4 clock cycles. Synchronizer performance is also analyzed when the two communicating clock domains are separated by long interconnect, incurring additional latencies.