An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reasoning about synchronization in GALS systems
Formal Methods in System Design
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Pausible clocking schemes have been proposed by GALSarchitects as a promising mechanism for reliable data transferbetween synchronous modules fed by low-speed independentclocks. In this paper, we argue that existingschemes are not well-suited for interfacing high-speed IPcores with large clock-distribution tree delay and high communicationrates. We propose an alternative interface circuitdesign for such IP cores that works with partial handshakebetween communicating modules and minimizes theperformance penalty of the sender and receiver. Our circuit,unlike pausible clocking, has a small probability of failure.