Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Power reduction in on-chip interconnection network by serialization
Proceedings of the 13th international symposium on Low power electronics and design
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Integration, the VLSI Journal
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner.