Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Power reduction in on-chip interconnection network by serialization
Proceedings of the 13th international symposium on Low power electronics and design
Integration, the VLSI Journal
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not based on including in each ring oscillator a synchronizing element (such as for instance an arbiter) which on one side can pause the clock and on the other side offers a handshake interface. Instead, we propose a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator. Since these clock signals also behave as handshake signals, handshake circuits can be used to synchronize the clocks.We demonstrate the technique in the context of processors and memories. All the designs have been simulated and showed functionally correct.