Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We explore the use of serialization in on-chip buses for reducing interconnect energy. Serialization reduces wire density and hence the coupling capacitance between adjacent data bits. This enables higher data rates, thus making it possible to send multiple data bits on a single wire within a single clock cycle. Energy reduction is brought about as a result of the decreased coupling capacitance, however this is offset by increased size and number of repeaters to obtain higher speed. A critical delay exists above which serialization is more energy efficient. We find this critical delay for a 2:1 serialization by solving an optimization problem formulated as minimization of power with serialization factor (1 or 2), area, bandwidth and frequency as constraints, and having repeater size, number of repeaters, and wire dimensions as design variables. We find that for delays above 40% of minimum delay for the wire, double pumping is more energy efficient across a range of technology nodes and supply voltages and matches well with a simple analytical derivation.