Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Adding Synchronous and LSSD Modes to Asynchronous Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALS at ETH Zurich: Success or Failure
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Demystifying Data-Driven and Pausible Clocking Schemes
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
GALS for Bursty Data Transfer based on Clock Coupling
Electronic Notes in Theoretical Computer Science (ENTCS)
Exploring Multi-Paradigm Modeling Techniques
Simulation
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring
Proceedings of the 49th Annual Design Automation Conference
Implementing constrained cyber-physical systems with IEC 61499
ACM Transactions on Embedded Computing Systems (TECS)
International Journal of Embedded and Real-Time Communication Systems
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area efficient asynchronous SDM routers using 2-stage clos switches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Quantifying the cost and benefit of latency insensitive communication on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
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For more than 20 years, significant research effort was concentrated on globally asynchronous, locally synchronous (GALS) design methodologies. But despite several successful implementations, GALS has had little impact on industry products. This article presents different GALS techniques and architectures. The authors also analyze the actual challenges and problems for wider adoption of the currently proposed GALS methods. Their analysis shows that significant improvement can be achieved in terms of system integration and EMI reduction. On the other hand, for power savings, only marginal improvements to the existing techniques can be expected. Additionally, introduction of a GALS approach leads to relatively small area increases, and in some cases even causes certain performance losses. The authors present major examples of GALS implementations. Finally, they outline some directions for future development of GALS techniques and their design flow. It is quite clear that the GALS design and test flow must be improved and more automated. Furthermore, the attendant performance degradations must be limited--for example, high data throughput must be ensured through very low hardware overhead for the GALS circuitry.