Digital systems engineering
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Enabling Technology for On-Chip Interconnection Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects
HOTI '09 Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/deserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit-serial links in parallel, mainly comes from the sharing of the novel serializer's control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail encoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity of the transmission. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissipation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics.