High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

Authors:
Rostislav Reuven Dobkin;Yevgeny Perelman;Tuvia Liran;Ran Ginosar;Avinoam Kolodny
Affiliations:
Israel Institute of Technology, Haifa;Israel Institute of Technology, Haifa;Israel Institute of Technology, Haifa;Israel Institute of Technology, Haifa;Israel Institute of Technology, Haifa
Venue:
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Year:
2007

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Abstract

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughput in 65nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a lowcrosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.