Communications of the ACM
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
The wave pipeline effect on LUT-based FPGA architectures
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimization techniques for FPGA-based wave-pipelined DSP blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Interconnection lengths and delays estimation for communication links in FPGAs
Proceedings of the 2008 international workshop on System level interconnect prediction
Global interconnections in FPGAs: modeling and performance analysis
Proceedings of the 2008 international workshop on System level interconnect prediction
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.