Circuit implementation of high-speed pipeline systems
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
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AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
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AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
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ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
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IEEE Transactions on Computers
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AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
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IEEE Transactions on Computers
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Regular 2D NASIC-based architecture and design space exploration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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There is widespread opinion that we are fast approaching the physical limit in speeds for computers. The grounds for such conclusions are traceable to signal propagation delays in interconnections, delays encountered in traversing several levels of combinatorial logic, and to systems organizations. Clearly, these areas must be addressed if we are to realize phenomenal improvements in computer logic speeds over the next decade. Subnanosecond logic circuits will be available; however, design innovations are needed to exploit this performance at the systems level.