High-performance CMOS system design using wave pipelining
High-performance CMOS system design using wave pipelining
Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance evaluation of asynchronous logic pipelines with data dependent processing delays
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
An Asynchronous 2-D Discrete Cosine Transform Chip
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Single-transistor transparent-latch clocking
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
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ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
The IBM system/360 model 91: floating-point execution unit
IBM Journal of Research and Development
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault tolerant clockless wave pipeline design
Proceedings of the 1st conference on Computing frontiers
Optimization techniques for FPGA-based wave-pipelined DSP blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The two-phase asynchronous wave-pipeline design style presented in this paper is targeted at VLSI systems operating at Giga rates where it is rather difficult and costly to maintain the synchronous paradigm. Its distinguishing properties are the use of a request signal only, simple latches and the inelastic wave-pipelined operation. The asynchronous wave-pipeline is found to have less overhead and to be more robust than the synchronous one. The same basic structure is suitable for both data and control. Buildings blocks of a distributed arithmetic-based 2D-DCT are shown. Simulations of circuits to be fabricated on a 0.6um CMOS process show throughput rates as high as 800$\,$MHz for the 2D-DCT.