Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A CMOS wave-pipelined image processor for real-time morphology
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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Double Pass Transistor Logic for High Performance Wave Pipeline Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Design and FPGA implementation of lifting scheme for 2D-DWT using wavepipelining
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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In this paper, techniques for efficient implementation of field-programmable gate-array (FPGA)-based wave-pipelined (WP) multipliers, accumulators, and filters are presented. A comparison of the performance of WP and pipelined systems has been made. Major contributions of this paper are development of an on-chip clock generation scheme which permits finer tuning of the frequency, a synthesis technique that reduces the area and latency by 25%, a placement utility that results in 10%-40% increase in speed and proposal of an interleaving scheme for filters that reduces the number of multipliers required by 50%. WP multipliers of size 2 × 6 and the filters using them are found to be 11% faster and require lower power than those using pipelined multipliers. Filters with higher order WP multipliers also operate with lower power at the cost of speed. The delay-register products of such filters are found to be about 60% lower than those using the pipelined multipliers. The paper also outlines applications of these techniques for the Spartan II FPGAs and a self-tuning scheme for optimizing the speed.