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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for automating this adjustment and they are evaluated by implementation of filters using a Distributed Arithmetic Algorithm (DAA) and sinewave generator using the COordinate Rotation DIgital Computer (CORDIC). Both the circuits are studied by adopting three schemes: wave-pipelining, pipelining, and nonpipelining. Xilinx Spartan II and Altera Cyclone II FPGAs with Nios II soft-core processor are used for implementation of the circuits with the BIST and SOC approaches, respectively. The proposed schemes increase the speed of the WP circuits by a factor of 1.19--2.6 compared to nonpipelined circuits. The pipelined circuits achieve higher speed than the WP circuits by a factor of 1.13--3.27 at the cost of increase in area and power. When both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for moderate logic depths. The observation regarding the dependence of the superiority of the WP circuits with regard to power dissipation on the logic depth is one of the major contributions of this article.