Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology

Authors:
Mehdi Alipour;Mohammad Haji Seyed Javadi;Ali Jahanian
Affiliations:
Qazvin Islamic Azad University, Qazvin, Iran;Qazvin Islamic Azad University, Qazvin, Iran;Shahid Beheshti University, G. C., Tehran, Iran
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

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Abstract

Asynchronous serial transceivers have been recently used for data multiplexing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the serial transmission but these links have not been exploited in FPGAs yet. In this paper, we present a new architecture corresponding with a routing algorithm to use the asynchronous wire multiplexing technique in FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (9.37% and 9.03%, respectively) by using the asynchronous wire multiplexing without any performance degradation in cost of a little overhead in area and computation time (2% and 0.84%, respectively)