NoC Communication Strategies Using Time-to-Digital Conversion
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Integration, the VLSI Journal
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous protocol converters for two-phase delay-insensitive global communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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A fast asynchronous shift register is used as the serializer and de-serializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR encoding. Acknowledgement is generated only at the word level, rather than bit by bit. The shift register is designed to achieve bit time of a single gate delay. It is based on a wave-pipelined control path and on transition latches. The circuit achieved 67 Gbps data rate when simulated on 65nm CMOS technology and was immune to in-die process variations of up to 10.