Communications of the ACM
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Asynchronous Design: An Enabler for Flexible Microelectronics
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
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As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive asynchronous protocols for robust system-level communication. However, in practice, it is extremely inefficient to build local asynchronous computation nodes with two-phase logic, hence four-phase (i.e., return-to-zero) computation blocks are typically used. This paper proposes two new architecture for a family of asynchronous protocol converters that translate between two- and four-phase protocols, thus facilitating robust system design using efficient global two-phase communication and local four-phase computation. A converter circuit is implemented and evaluated a 0.18 micron TSMC process through post-layout simulation, assuming both a small computation block (8 × 8 combinational multiplier) and an empty computation block (FIFO stage).