Communications of the ACM
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Sequencer circuits for VLSI programming
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Logical design of macromodules
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
Concurrency-oriented optimization for low-power asynchronous systems
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Asynchronous First-in First-out Queues
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Sequencer circuits for VLSI programming
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-power Asynchronous Data-path for a FIR Filter Bank
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance-driven syntax-directed synthesis of asynchronous processors
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing
Journal of Signal Processing Systems
GALS Test Chip on 130nm Process
Electronic Notes in Theoretical Computer Science (ENTCS)
Scalable multi-input-multi-output queues with application to variation-tolerant architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous protocol converters for two-phase delay-insensitive global communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural optimization for low-power nonpipelined asynchronous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Single-rail handshake circuits are introduced as a cost effective implementation of asynchronous circuits. Compared to double-rail implementations, the circuits are smaller, faster, and more energy-efficient. Furthermore, in contrast to common belief, all four phases of the four-phase handshake protocol can be productive. An important selling point for single-rail circuits is that they can be implemented in any (generic) standard-cell library. This facilitates technology migration and makes asynchronous circuits a potential technology of choice for low-power applications.