Communicating sequential processes
Communicating sequential processes
Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
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A fully asynchronous Reed-Solomon decoder for the DCC player has been designed in the VLSI programming language Tangram. The main design aim was minimal power dissipation. The design decisions leading to a low-power cost-effective design are discussed. The asynchronous circuit has been fabricated and successfully incorporated in a working DCC system. We estimate that this chip is less than 20% larger in area and at a supply voltage of 5 V five times more economic in power consumption than existing clocked implementations. The chip has two power pins: one for a low and one for a high voltage. Depending on the work-load the circuit dynamically selects one of the two supply voltages by means of a power switch. If the chip is operated at 1.5 V and 5 V, the power dissipation is further reduced by a factor 20.