Communicating sequential processes
Communicating sequential processes
Logic testing and design for testability
Logic testing and design for testability
Syntax-directed translation of concurrent programs into self-timed circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Sequencer circuits for VLSI programming
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Testing delay faults in asynchronous handshake circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%.