Communications of the ACM
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A generalized state assignment theory for transformations on signal transition graphs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance-driven synthesis of asynchronous controllers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A communicating Petri net model for the design of concurrent asynchronous modules
DAC '94 Proceedings of the 31st annual Design Automation Conference
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Communicating sequential processes
Communications of the ACM
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Introduction to VLSI Systems
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Practical Asynchronous Controller Design
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Peephole Optimization of Asynchronous Macromodule Networks
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Sequencer circuits for VLSI programming
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
Proceedings of the 39th annual Design Automation Conference
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Logic Synthesis of Handshake Components Using Structural Clustering Techniques
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
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Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown to generate efficient asynchronous implementations. However, for control-dominated designs where the data processing parts play a relatively minor role, we believe the solutions produced by pure syntax directed translation methods may be significantly improved. In this paper, we consider the problem of resynthesizing the control parts of the syntax directed translation solutions by means of STG based algorithmic synthesis approaches. This involves a strategy for partitioning between the control and data processing parts, algorithms for reconstructing the STGs from the control partitions, and a strategy for resynthesizing these reconstructed STGs using existing STG-based synthesis approaches. We show with a realistic design experiment that our control resynthesis approach can offer significant improvements over pure syntax directed translation solutions.