Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Synthesis of Timed Asynchronous Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Practical Asynchronous Controller Design
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Estimation and bounding of energy consumption in burst-mode control circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
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We examine the implications of a new hazard-free combinational logic synthesis method, which generates multiplexor trees from binary decision diagrams (BDDs)—representations of logic functions factored recursively with respect to input variables—on extended burst-mode asynchronous synthesis. First, the use of the BDD-based synthesis reduces the constraints on state minimization and assignment, which reduces the number of additional state variables required in many cases. Second, in cases where conditional signals are sampled, it eliminates the need for state variable changes preceding output changes, which reduces overall input to output latency. Third, selection variables can easily be ordered to minimize the latency on a user-specified path, which is important for optimizing the performance of systems that use asynchronous components. We present extensive evaluations showing that, with only minimal optimization, the BBD-based synthesis gives comparable results in area with our previous exact two-level synthesis method. We also give a detailed example of the specified path optimization.