Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The design of a high-performance cache controller: a case study in asynchronous synthesis
Integration, the VLSI Journal - Special issue on asynchronous systems
Designing an Asynchronous Communications Chip
IEEE Design & Test
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance-driven synthesis of asynchronous controllers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Estimation of energy consumption in speed-independent control circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automated energy calculation and estimation for delay-insensitive digital circuits
Microelectronics Journal
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This paper describes two techniques to quantify energy consumption of burst-mode asynchronous (clock-less) control circuits. The circuit specifications considered are extended burst-mode specifications, and the implementations are multi-level logic implementations whose outputs are guaranteed to be free of any voltage glitches (hazards). Both techniques use stochastic analysis to combine a small number of simulations in order to quantify average energy per external signal transition. The first technique uses N-valued simulation to derive mathematically tight upper and lower bounds of energy consumption. Using this technique we bound the effect of hazards under all possible operating conditions and environments for a given circuit. Additionally, to drive synthesis tools for low-power, we propose a second technique that uses fixed-delay simulation to derive a realistic estimate of energy consumption within our derived upper and lower bounds. We demonstrate the feasibility of both these techniques on a variety of burst-mode control circuits used in an industrial-quality chip. Our preliminary results indicate that less than 5% of the power of typical multi-level burst-mode circuits can be attributed to hazards.