DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Communications of the ACM
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
Estimation and bounding of energy consumption in burst-mode control circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Technology mapping of timed circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Computing the area versus delay trade-off curves in technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power efficient technology decomposition and mapping under an extended power consumption model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of hazard-free asynchronous circuits with bounded wire delays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Logic Synthesis and Verification
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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This paper presents technology mapping techniques that optimize for average case delay of asynchronous burst-mode control circuits. First, the specification of the circuit is analyzed using stochastic techniques to determine the relative frequency of occurrence of each state transition. Then, subject to timing and area constraints, the technology mapper minimizes the sum of the cycle times of the state transitions, weighted by their relative frequencies. Unlike other technology mappers, our mapper is based on the single step transition model for delay which finds the true critical paths, avoiding the false path problem.