A technique for synthesizing distributed burst-mode circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
An efficient divide and conquer algorithm for exact hazard free logic minimization
Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
From STG to Extended-Burst-Mode Machines
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Asynchronous Microengines for Efficient High-level Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
CASCADE: a tool kernel supporting a comprehensive design method for asynchronous controllers
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
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