Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Synthesis of speed-independent circuits from STG-unfolding segment
DAC '97 Proceedings of the 34th annual Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Efficient state assignment framework for asynchronous state graphs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A high-performance asynchronous SCSI controller
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Covering conditions and algorithms for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structural methods for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic synthesis of extended burst-mode circuits. II. (Automatic synthesis)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient algorithms for exact two-level hazard-free logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Asynchronous controllers are very efficient to operate as high performance interfaces in heterogeneous synchronous/ asynchronous systems. Asynchronous controllers may be designed to operate either in the generalized fundamental mode (GFM) or in the input-output (I/O) mode. The latter are more robust to temperature variation and technology migration and may operate in faster environments. However, none of the existing synthesis tools, targeting circuits that operate in the I/O mode accept non-monotonic level sensitive signals (usually adopted to describe conditions in heterogeneous systems). Another limitation of these synthesis tools concerns the number of signals that may be present in the initial specification. This limitation comes from the input description that must be either a signal transition graph (STG) or a state graph (SG). In this article we present Miriã-SI, an extension of the Miriã-GFM synthesis tool that can synthesize such circuits. It starts from a state transition description known as multi-burst graph that is able to accept up to 200 signals. Non-monotonic signals are nicely handled. The resulting controllers, implemented in the feedback set-dominant latch architecture are guaranteed to be hazard free.