Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
GALS Test Chip on 130nm Process
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic synthesis of computation interference constraints for relative timing verification
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Enhanced GALS techniques for datapath applications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
| Hi-index | 0.03 |
We introduce a new design style called extended burst-mode. The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machines and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using existing methods. Our implementation of extended burst-mode machines uses standard CMOS logic, generates low-latency outputs, and guarantees freedom from hazards at the gate level. In Part I, we formally define the extended burst-mode specification, provide an overview of the synthesis methods, and describe the hazard-free synthesis requirements for two different next-state logic synthesis methods: two-level sums-of-products implementation and generalized C-elements implementation. We also present an extension to existing theories for hazard-free combinational synthesis to handle nonmonotonic input changes