Communications of the ACM
Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Communicating sequential processes
Communications of the ACM
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hierarchical module expansion in a VHDL behavioural synthesis system
Electronic chips & systems design languages
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Two-Phase Asynchronous Pipeline Control
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Level Asynchronous System Design Using the ACK Framework
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET3i - An Asynchronous System-on-Chip
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
SPA " A Synthesisable Amulet Core for Smartcard pplications
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
Architectural Synthesis of Timed Asynchronous Systems
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
On-line testing of statically and dynamically scheduled synthesized systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic synthesis of extended burst-mode circuits. II. (Automatic synthesis)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floating-point behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The design of an asynchronous blocksorter
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A VHDL-based design methodology for asynchronous circuits
WSEAS Transactions on Circuits and Systems
The design of a simple asynchronous processor
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
The design of sharing resources for asynchronous systems
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
An evaluation for the design of asynchronous systems
WSEAS Transactions on Circuits and Systems
An optimization for the design of a simple asynchronous processor
WSEAS Transactions on Computers
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Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional units); and 3) binding (the mapping of the functional units onto physical cells). Optimization is usually achieved by intelligent manipulation of these three steps in some way. Key to the operation of such a system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronizing clock. The maximum clock speed is dictated by the slowest time slot. (This is the timeslot containing the longest combinational logic delay.) Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of "ready" and "acknowledge," the control graph becomes a disjoint set of single-state machines--it effectively disappears, with the consequence that the timeslot-timeslot transitions become self controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes selftiming: asynchronous. This paper describes a behavioral asynchronous synthesis system based on this concept that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level description). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed.