Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation

Authors:
Naohiro Hamada;Hiroshi Saito
Affiliations:
The University of Aizu, Fukushima, Japan;The University of Aizu, Fukushima, Japan
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

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Abstract

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation which iteratively applies behavioral synthesis and floorplanning to obtain an optimum circuit in terms of performance under given design constraints. We evaluate the effectiveness of the proposed method through synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to ones without considering timing constraints. Also, the proposed method is effective to reduce the number of timing violations.