Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Analysis Driven Synthesis of Asynchronous Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath
Proceedings of the 17th ACM Great Lakes symposium on VLSI
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Statistical makespan analysis in asynchronous datapath synthesis
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Behavioral synthesis of asynchronous circuits using syntax directed translation as backend
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High level synthesis of asynchronous circuits from data flow graphs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
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This paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponentially with respect to the size of the given data flow graph, pruning techniques are introduced which dramatically improve runtime without significantly affecting the quality of the results. Using a combination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some high-level synthesis benchmark circuits and an industrial example.