TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Architectural Synthesis of Timed Asynchronous Systems
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Statistical Analysis Driven Synthesis of Asynchronous Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Hi-index | 0.00 |
In this paper, we propose an extended model of register-sharing in a dual-rail two-phase asynchronous datapath, which provides us with a larger solution space of resource sharing. We introduce a new type of register which is driven by data to be latched and a control signal. By using this type of register, multiple data can share the same register aggressively in a dual-rail two-phase asynchronous datapath.