Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Architectural Synthesis of Timed Asynchronous Systems
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
An Introduction to High-Level Synthesis
IEEE Design & Test
A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
Multi-token resource sharing for pipelined asynchronous systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we explore the problem of scheduling and allocation for asynchronous systems under latency, area, energy, and power constraints, and present exact methods for minimizing an implementation for either latency, area, or energy. This approach utilizes the the branch-and-bound strategy developed in [1], but targets a much more robust solution space by incorporating many-to-many mappings of operations to function units and energy and power considerations into the search space. Unlike many recent solutions that adapt synchronous methods to the asynchronous realm, our approach specifically targets the asynchronous domain. As a result, our solver's complexity and performance are independent of the discretization of time. We illustrate the effectiveness of this approach by running 36 different test cases on small and large input specifications; results are produced in 60 seconds or less for each example.